AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, V IN = 12V, V CC = V DD1 = V DD2 = SHDN = PGD_IN = 5V, V DDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T A = 0°C to +85°C , unless otherwise noted.
Typical values are at T A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2-WIRE SVI BUS LOGIC INTERFACE
SVI Logic Input Current
SVI Logic Input Threshold
SVC, SVD
SVC, SVD, rising edge,
hysteresis = 0.15V DDIO
-1
0.3 x
V DDIO
+1
0.7 x
V DDIO
μA
V
SVC Clock Frequency
START Condition Hold Time
Repeated START Condition
Setup Time
STOP Condition Setup Time
f SVC
t HD,STA
t SU,STA
t SU,STO
160
160
160
3.4
MHz
ns
ns
ns
A master device must internally provide a
hold time of at least 300ns for the SDA
Data Hold
t HD,DAT
signal (referred to the V IL of SCK signal) to
70
ns
bridge the undefined region of SCL’s falling
edge
Data Setup Time
SVC Low Period
SVC High Period
t SU,DAT
t LOW
t HIGH
10
160
60
ns
ns
ns
SVC/SVD Rise and Fall Time
Pulse Width of Spike Suppression
t R , t F
Measured from 10% to 90% of V DDIO
Input filters on SVD and SVC suppress
noise spikes less than 50ns
20
40
ns
ns
INPUTS AND OUTPUTS
Logic Input Current
Logic Input Threshold
SHDN , PGD_IN
PRO , OPTION
SHDN , rising edge, hysteresis = 225mV
-1
-3
0.8
+1
+3
2.0
μA
V
High
V CC -
0.4
Four-Level Input-Logic Levels
OPTION
Open
3.15
3.85
V
REF
Low
1.65
2.35
0.4
Tri-Level Input-Logic Levels
PRO
High
Open
V CC -
0.4
3.15
3.85
V
Low
0.4
PGD_IN Logic Input Threshold
PGD_IN
0.3 x
V DDIO
0.7 x
V DDIO
V
Low state, I SINK = 3mA
0.4
NBSKP Logic Output Voltage
High state, I SOURCE = 3mA
V CC -
0.4
V
6
_______________________________________________________________________________________
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